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po wer ma nage m ent & m ul ti m ark et dat as he et rev. 1.2, 2015-09-23 icl5101 resonant controller ic with pfc for led driver
icl5101 datasheet 2 rev. 1.2, 2015-09-23 resonant controller ic with pfc for led driver product highlights ? supports universal input and wide output range ? low count of external components supporting small form factors and improved reliability ? all parameters set by simple resistors only ? supports outdoor use by extended junction temperature range from -40 c to +125 c ? stable low load operation mode down to 0.1 % of nominal power rating ? comprehensive set of protection features incl. external over temperature protection and capacitive load protection to increase system safety ? ultra-fast time to light < 200 ms ? power factor correction > 99 %, thd < 5 % ? high efficiency up to 94 % pfc feature set ? pfc in crcm mode during nominal load and dcm mode in low load condition down to 0.1 % for operation without audible noise ? adjustable thd compensation of ac input current even in dcm operation for lowest thd ? adjustable pfc current limitation resonant half bridge feature set ? fully integrated 650 v high-side driver ? self-adaptive dead time control of the integrated half bridge driver 500 ns ? 1.0 s ? detection of capacitive operation, overload, short circuitry and output overvoltage ? improved operation control in magnetic saturation during start-up ? advanced error detection control applications ? led driver, e.g. commercial or residential lighting systems > 50 w ? integrated electronic control gear for led luminaires description the led resonant controller icl5101 is designed to control resonant converter topologies. the pfc stage operates in crcm and dcm mode, supporting low load conditions. integrated high and low side drivers assure a low count of external components, enabling small form factor designs. icl5101 parameters are adjusted by simple resistors only, this being the ideal choice to ease the design-in process. a comprehensive set of protection features ensures that the led driver detects fault conditions, protecting both the led driver and the led load. figure 1shows a typical application circuit of a 110 w constant voltage led driver. figure 1 typical application product type package icl5101 pg-dso-16-23 pg-dso-16-23 r 8 r f m n . a . n . a . v c c o v p g n d i c l 5 1 0 1 o t p v r 1 ? r 1 1
icl5101 table of contents datasheet 3 rev. 1.2, 2015-09-23 table of contents resonant controller ic with pfc for led driver.................................................................................................2 1 pin configuration and description...................................................................................................4 1.1 pg-dso-16-23 package......................................................................................................................4 1.2 pin configuration for pg-dso-16-23 ..................................................................................................4 1.3 pin set-up ...........................................................................................................................................5 1.4 pin functionality ..................................................................................................................................6 2 functional description ....................................................................................................................10 2.1 introduction.........................................................................................................................................10 2.1.1 uvlo to soft start..............................................................................................................................13 2.1.2 soft start to run mode.......................................................................................................................14 2.2 detection stage..................................................................................................................................15 2.2.1 detection of overtemperature............................................................................................................15 2.2.2 detection of output overvoltage........................................................................................................15 2.2.3 detection of capacitive mode operation ...........................................................................................15 2.2.4 surge protection.................................................................................................................................16 2.2.5 self-adapting dead time during gate drive activity between hs and ls ........................................17 2.2.6 short term bus under voltage...........................................................................................................18 2.2.7 long-term bus under voltage ...........................................................................................................19 2.3 pfc preconverter...............................................................................................................................20 2.3.1 operation modes of the pfc converter ............................................................................................20 2.3.2 pfc bus overvoltage and open loop...............................................................................................21 2.3.3 pfc bus voltage levels 95 % and 75 %...........................................................................................21 2.3.4 pfc structure of mixed signals .........................................................................................................22 2.3.5 thd correction via zero crossing detection singal..........................................................................23 2.4 state diagram ....................................................................................................................................26 2.4.1 monitoring of features versus operating mode.................................................................................26 2.4.2 fault condition ? flow chart fault f latch off / single restart / restart.......................................27 2.4.3 fault condition ? flow chart fault a auto restart ............................................................................28 2.4.4 fault condition ? flow chart fault u bus voltage ...........................................................................29 2.4.5 protection matrix ................................................................................................................................30 3 electrical characteristics ................................................................................................................31 3.1 absolute maximum ratings ...............................................................................................................31 3.2 operating range ................................................................................................................................33 3.3 characteristics power supply section ...............................................................................................34 3.4 characteristics of pfc section ..........................................................................................................34 3.4.1 pfc current sense (pfccs) ............................................................................................................34 3.4.2 pfc zero current detection (pfczcd) ............................................................................................35 3.4.3 pfc voltage sensing bus (pfcvs) ..................................................................................................35 3.4.4 pfc pwm generation .......................................................................................................................35 3.4.5 pfc gate drive (pfcgd) ..................................................................................................................36 3.5 characteristics of inverter section .....................................................................................................36 3.5.1 low-side current sense (lscs) .......................................................................................................36 3.5.2 low-side gate drive (lsgd).............................................................................................................37 3.5.3 inverter minimum run frequency (rfm) ..........................................................................................37 3.5.4 overtemperature protection (otp) ....................................................................................................38 3.5.5 overvoltage protection (ovp)............................................................................................................38 3.5.6 high side gate drive (hsgd)............................................................................................................39 3.6 timer section .....................................................................................................................................39 4 application example ........................................................................................................................40 4.1 schematic...........................................................................................................................................40 5 outline dimensions .........................................................................................................................41
icl5101 pin configuration and description datasheet 4 rev. 1.2, 2015-09-23 1 pin configuration and description the pin configuration is shown in figure 2 and pin functionality table 1. the pin functions are described below. 1.1 pg-dso-16-23 package figure 2 pin configuration 1.2 pin configuration for pg-dso-16-23 symbol pin function lsgd 1 low-side gate drive lscs 2 low-side current sense signal vcc 3 chip supply voltage gnd 4 ic gnd pfcgd 5 pfc gate drive pfccs 6 pfc current sense signal pfczcd 7 pfc zero crossing detection pfcvs 8 pfc voltage sensing rfm 9 set run frequency n.a. 10 not applicable: leave pin open n.a. 11 not applicable: set to gnd ovp 12 overvoltage protection of secondary output otp 13 over temperature protection hsgnd 14 high-side gnd hsvcc 15 high-side supply voltage hsgd 16 high-side gate drive
icl5101 pin configuration and description datasheet 5 rev. 1.2, 2015-09-23 1.3 pin set-up the pin set-up of icl5101 is shown in figure 3. figure 3 pin set-up the schematic in figure 3 shows a typical pin set-up for a pfc / llc converter i c l 5 1 0 1
icl5101 pin configuration and description datasheet 6 rev. 1.2, 2015-09-23 1.4 pin functionality table 1. pin definitions and functions symbol pin function lsgd 1 low - s ide g ate d rive the gate of the low-side mosfet in an resonant inverter topology is controlled by this pin. there is an active l-level during uvlo (under voltage lockout) and a limitation of the max h-level at 11.0 v during normal operation. in order to turn on the mosfet softly (with a reduced di drain /dt), the gate voltage rises typically within 245 ns from l-level to h-level. the fall time of the gate voltage is less than 50 ns in order to turn off quickly. this measure produces different switching speeds during turn-on and turn- off as it is usually achieved with a diode parallel to a resistor in the gate drive loop. it i s r e c o m m e n d e d t o u s e a r e s i s t o r o f t y p i c a l l y 1 0 b e t w e e n t h e drive pin and gate in order to avoid oscillations and in order to shift the power dissipation when discharging the gate capacitance into this resistor. the typical dead time between the lsgd signal and hsgd signal is self-adapting between 500 ns and 1.0 s. lscs 2 low-side current sense signal this pin is directly connected to the shunt resistor, which is located between the source terminal of the low-side mosfet of the inverter and ground. internal clamping structures and filtering measures allow sensing of the source current for the low side inverter mosfet without additional filter components. there is a first threshold of 0.8 v. if this threshold is exceeded for longer than 500 ns during run mode, an inverter overcurrent is detected , which causes a latched shutdown of the ic. the s aturation control is activated if the sensed slope at the lscs pin reaches typical values of 205 mv/s 25 mv/s and exceeds the 0.8 v threshold. the saturation regulator is now continuously monitored by the lscs pin during saturation control and extended saturation control mode. in saturation control the regulator is designed to handle a choke operation in saturation. if the sensed current signal exceeds a second threshold of 1.6 v for longer than 500 ns before entering the run mode, the ic changes over into a latched shutdown. there are further thresholds active at this pin during run mode that detects capacitive mode operation. a voltage level below -50 mv indicates faulty operation (operation below resonance). a second threshold at 2.0 v senses even short over currents during turn- on of the high-side mosfet such as is typical for reverse recovery currents of a diode. if one of these comparator thresholds indicates incorrect operating conditions for longer than 620 s (overcurrent / operation below re sonance) in run mode, the ic turns off the gate s and changes to fault mode due to detected capacitive mode operation (non-zero voltage switching). the threshold of -50 mv is also used to adjust the dead time between turn- off and turn-on of the resonant drivers in a range of 500 ns to 1.0 s during all operating modes. vcc 3 chip s upply v oltage this pin provides the power supply of the ground- related section of the ic. there is a turn-on threshold at 14.0 v and a uvlo threshold at 10.6 v. the upper supply voltage level is 17.5 v. there is an internal zener diode clamping v cc at 16.3 v (at i vcc = 2 ma typically). the maximum zener current is internally limited to 5 ma. an external zener diode is required f or higher current levels. current consumption during uvlo and during fault mode is less than 170 a. a ceramic capacitor close to the supply and gnd pin is required in order to act as a low-impedance power source for gate drive and logic signal currents. in the event of a short interruption to the mains supply, feed the start-up current (160 a) from the bus voltage.
icl5101 pin configuration and description datasheet 7 rev. 1.2, 2015-09-23 symbol pin function gnd 4 ic gnd this pin is connected to ground and represents the ground level of the ic for the supply voltage, gate drive and sense signals. pfcgd 5 pfc g ate d rive the gate of the mosfet in the pfc preconverter designed in boost topology is controlled by this pin. there is an active l- level during uvlo and a limitation of the max h-level at 11.0 v during normal operation. in order to turn on the mosfet softly (with a reduced di drain /dt), the gate drive voltage rises within 245 ns from l-level to h-level. the fall time of the gate voltage is l e s s t h a n 5 0 n s i n o r d e r t o t u r n o f f q u i c k l y . a r e s i s t o r o f t y p i c a l l y 1 0 i s recommended between the drive pin and gate in order to avoid oscillations and in order to shift the power dissipation when discharging the gate capacitance into this resistor. the pfc section of the ic controls a boost converter as a pfc preconverter in discontinuous conduction mode (dcm). typically, the control starts with gate drive pulses with a fixed on-time of typically 4.0 s at v acin = 230 v, increasing up to 24 s and with an off-time of 47 s. as soon as sufficient zero current detector (zcd) signals are available, the operation mode changes from fixed frequency operation to operation with variable frequency. the pfc works in critical conduction mode operation (crcm) when rated and/or medium load conditions are present. that means triangular- shaped currents in the boost converter choke without gaps and variable operating frequency. during low load (detected by an internal compensator) we obtain operation with discontinuous conduction mode (dcm) ? that means triangular-shaped currents in the boost converter choke with gaps when reaching the zero current level and variable operating frequency in order to avoid steps in the consumed line current. pfccs 6 pfc current sense signal the voltage drop across a shunt resistor located between the source of the pfc mosfet and gnd is sensed with this pin. if the level exceeds a threshold of 1.0 v for longer than 200 ns, the pfc gate drive is turned off as long as the zero current detector (zcd) enables a new cycle. if no zcd signal is available within 52 s after turn-off of the pfc gate drive, a new cycle is initiated from an internal start-up timer. pfczcd 7 pfc z ero c rossing d etection this pin senses the point of time when the current through the boost inductor becomes zero during the off-time of the pfc mosfet in order to initiate a new cycle. the moment of interest appears when the voltage of the separate zcd winding changes from positive to negative level, which represents a voltage of zero at the inductor windings and therefore the end of current f low from the lower input voltage level to the higher output voltage level. there is a threshold with hysteresis, 1.5 v for increasing level, 0.5 v for decreasing level, which detects the change in inductor voltage. a resistor connected between the zcd winding and pin 7 limits the sink and source current of the sense pin when the voltage of the zcd winding exceeds the internal clamping levels (typically 6.3 v and -2.9 v @ 5 ma) of the ic. if the sensed voltage level of the zcd winding is not sufficient (e.g. during start- up), an internal start-up timer will initiate a new cycle every 52 s after turn- off of the pfc gate drive. the source current out of this pin during the on- time of the pfc-mosfet indicates the voltage level of the ac supply voltage. duri ng low input voltage levels, the on-time of the pfc- mosfet is enlarged in order to minimize gaps in the line current during zero crossing of the line voltage and improve the thd (total harmonic distortion) of the line current. optimization of the thd is po ssible by trimming of the resistor between this pin and the zcd winding in combination with the i nductance and used pfc mosfet.
icl5101 pin configuration and description datasheet 8 rev. 1.2, 2015-09-23 symbol pin function pfcvs 8 pfc voltage sensing the intermediate circuit voltage (bus voltage) at the smoothing capacitor is sensed by a resistive divider at this pin. the internal reference voltage for the rated bus voltage is 2.5 v. there are further thresholds at 0.3125 v (12.5 % of the rated bus voltage) for detection of open control loop and at 1.875 v (75 % of the rated bus voltage) for detection of under voltage, and at 2.725 v (109 % of the rated bus voltage) for detection of overvoltage. the overvoltage threshold operates with a hysteresis of 100 mv (4 % of the rated bus voltage). the bus voltage is sensed at 95 % (2.375 v) f or detection of a successful start- up. it is recommended to use a small capacitor between this pin and gnd as a spike suppression filter. in run mode, pfc overvoltage stops the pfc gate drive within 5 s. as soon as the bus voltage is less than 105 % of the rated level, the gate drives are enabled again. if the overvoltage lasts for longer than 625 ms, an inverter overvoltage is detected and turns off the inverter gate drive s also. this causes a power-down and a power-up when v bus < 109 %. a bus under- (v bus > 75 %) or inverter overvoltage during run mode is handled as fault bus. in this situation the ic changes to power- down mode and generates a delay of 100 ms with an internal timer. then start- up conditions are checked and if valid, a further start-up is initiated. if start- up conditions are not valid, a further delay of 100 ms is generated. this procedure is repeated a maximum of seven times. if a start- up is successful wi thin these seven cycles, the situation is interpreted as a short interruption of the mains supply. rfm 9 set minimum run frequency a resistor from this pin to ground sets the operating frequency of the inverter during run mode. the typical run frequency range is 20 khz to 120 khz @ - 40c and 130khz @ - 25c . the set resistor r_rfm can be calculated based on the run frequency f rfm according to the equation: run rfm f hz r ? ? ? 8 10 5 n.a. 10 not applicable: leave pin open n.a. 11 not applicable: set to ic gnd as short as possible ovp 12 over voltage protection of output voltage in order to prevent overvoltage at the output stage ? in the case of a floating led ?overvoltage protection at pin 12 can be activated. use a r esistor and a ceramic capacitor con nected to the auxiliary winding in order to sense the voltage level at the auxiliary winding. during run mode, the auxiliary winding is monitored by a sensing current proportional to the auxiliary voltage. if the peak-to-peak voltage at this pin exceeds a threshold of 210 app for longer than 620 s, overvoltage is detected. this function can be disabled by setting pin 12 to gnd. otp 13 over temperature protection in order to prevent over temperature of the system, activate the over temperature protection at the otp pin. use a temperature- dependent resistor and a ceramic capacitor connected to gnd for activation. there is a threshold of 3.2 v at the otp pin during active run mode. if the voltage rises above this threshold for longer than 620 s, the ic detects over temperature and changes to the latched fault mode. the latch mode is ended automatically by power-up or uvlo. this function can be disabled by setting pin 13 to gnd.
icl5101 pin configuration and description datasheet 9 rev. 1.2, 2015-09-23 symbol pin function hsgnd 14 high-side gnd this pin is connected to the source terminal of the high-side mosfet, which is also the node of high-side and low- side mosfet. this pin represents the floating ground level of the high-side driver and the high-side supply. hsvcc 15 high-side supply voltage this pin provides the power supply of the high-side ground- related section of the ic. an external capacitor between pins 14 and 15 acts like a floating battery, which has to be recharged cycle by cycle via a high- voltage diode from the low-side supply voltage during the on-time of the low- side mosfet. a uvlo threshold with hysteresis enables the high-side section at 10.4 v and disables it at 8.6 v. hsgd 16 high-side gate drive the gate of the high-side mosfet in an resonant inverter topology is controlled by this pin. there is an active l- level during uvlo and a limitation of the max h- level at 11.0 v during normal operation. the switching characteristics are the same as described for lsgd (pin 2). it is r e c o m m e n d e d t o u s e a r e s i s t o r o f a b o u t 1 0 b e t w e e n t h e d r i v e p i n a n d g a t e in order to avoid oscillations and in order to shift the power dissipation when discharging the gate capacitance into this resistor. the dead time between the lsgd signal and hsgd signal is self-adapting between 500 n s and 1.0 s (typically).
icl5101 functional description datasheet 10 rev. 1.2, 2015-09-23 2 functional description the functional description provides an overview of the integrated functions, features and their relationships. the parameters and equations provided are based on typical values at t a = 25 c. the corresponding minimum and maximum values are shown in the electrical characteristics. 2.1 introduction the icl5101 is a high-performance mixed-signal controller for led and smps applications. the ic is designed for a power factor correction (pfc) close to 1, low thd below 5 %, a maximum efficiency up to 94 % plus and a minimal design-in phase in wide and narrow range designs. furthermore, all parameters are valid in an extended temperature range from ?40 c up to 125 c ? especially frequency and timing. the controller utilizes a variety of protection features, including saturation control during start-up of the resonant converter, adjustable over temperature, along with open and short load conditions.
icl5101 functional description datasheet 11 rev. 1.2, 2015-09-23 figure 4 operating flowchart for led applications after 130s & v bus > 12,5% & v bus < 105% vcc < vccon(14.0v) otp detection v bus > 95% within 80ms vcc > 10.6v v bus < 12,5% or v bus > 105% after t_blanking uvlo vcc < 10.6v icc < 130a monitoring vcc > 10.6v icc < 160a power-up gate drives off vcc > 14.0v icc approx 6.0ma start-up inverter gates on pfc gate on 17.5v> vcc >10.6v f_inv = f_fixed softstart 17.5v> vcc >10.6v f_fixed => f_run saturation control timeout 237ms 17.5v> vcc >10.6v f = f_run extended sat control 17,5v> vcc >10.6v f = f_run run 17.5v> vcc >10.6v f = f_run complete monitoring fault 17.5v> vcc >10.6v icc < 170a gate drives off see protection functions see timing and handling of fault conditions vcc < 10.6v f = 135khz (fixed) frequency: f = 135khz (fix) t_start-uptyp ~ 12ms f = 135khz (fixed) frequency decrease: f = 135khz to f_run (set) t_ss = 11mstyp (digital) f = f_run (set) t_saturationcontroltyp = 45ms no impact on time to light t_blanking = 625ms operating flow chart icl5101
icl5101 functional description datasheet 12 rev. 1.2, 2015-09-23 start-up the device is powered through the vcc pin. all device supply voltages are internally generated from vcc voltage. typical start-up procedure below figure 5 shows a typical start-up procedure of the device. the following subsections describe the phases in detail. figure 5 typical start-up procedure run mode mode / time frequency / output voltage saturation control 135 khz v out = 100% 0 khz v cc = 17.5 v v cc = 14.1 v v cc = 10.6 v monitoring uvlo v lsgd / v cc v cc v cc = 0 v v pfcvs mode / time mode / time 100 % v pfcvs v dcin 60ms 35ms 10-80ms 11ms 40 - 237ms 625ms 45 khz low side gate drive f startup_fix f run_set v out = 90%
icl5101 functional description datasheet 13 rev. 1.2, 2015-09-23 2.1.1 uvlo to soft start this section describes the operating flow from uvlo to soft start in detail ? start-up procedure from uvlo to soft start figure 6. the control of the led ballast is able to start the operation in less than 100 ms (time to light ic is in active mode). this is achieved by the low current consumption during uvlo (i vcc = 130 a) and start-up hysteresis (i vcc = 160 a ? defines the start-up resistor) phases. the chip supply stage of the ic is protected against overvoltage via an internal zener clamping network, which clamps the voltage at 16.3 v and allows a current of 2.5 ma. for clamping currents above 2.5 ma, an external zener diode from vcc to gnd is required. figure 6 start-up procedure from uvlo to soft start if v cc exceeds the 10.6 v level and stays below 14.0 v (start-up hysteresis), the ic checks whether the pcb temperature is experiencing over temperature or an output overvoltage is present. over temperature is checked from a source current of typically i otp3 = - 21.3 a out of pin 13 otp (i otp ). this current produces a voltage drop of v otp < 1.6 v (temperature is ok). over temperature is detected if the voltage at the otp pin exceeds the v otp > 1.6v threshold (v otp ). the output overvoltage is checked by a current of typically i ovp > 12 a via resistors r12 into the ovp pin 12. output overvoltage is detected if there is no sink current into the ovp pin. this causes a higher source current out of the otp pin (typically 42.6 a / 35.4 a) in order to exceed v otp > 1.6 v. in the case of over temperature or overvoltage, the ic keeps monitoring until there is an adequate voltage from the otp or ovp pin. v out = 90% v cc 16.0 v 14.0 v 10.6 v uvlo soft start i vcc 130 a 1.6 v v otp i otp - 21.3 a i ovp > 18 a < 160 a < 6.0 ma + i gate < 210a pp v pfcvs 95 % 30 % 17.5 v 100 % 135 khz f startup frequency / v out monitoring start up v pfcvs
icl5101 functional description datasheet 14 rev. 1.2, 2015-09-23 when v cc exceeds the 14.0 v threshold ? by the end of the start-up hysteresis ? the ic waits for 80 s and senses the bus voltage. when the rated bus voltage is in the corridor of 12.5 % < v busrated < 105 %, the ic powers up. the ic initiates an uvlo when the chip supply voltage is below v cc < 10.6 v. as soon as the condition of a power-up is fulfilled, the ic starts the inverter gate operation with an internal fixed start-up frequency of 135 khz. the pfc gate drive starts with a delay of app. 300 s. then the bus voltage will be checked for a rated level above 95 % for duration of 80 ms. now, the ic enters the soft start phase and shifts the frequency from the internal fixed start-up frequency of 135 khz down to the set run frequency. 2.1.2 soft start to run mode this section describes the operating flow from soft start to run mode in detail. after the soft start phase is finished, the saturation control phase is entered. figure 7 start-up procedure from soft start to run mode during saturation control ( start-up procedure from soft start to run mode figure 7), the operating frequency of the inverter is shifted downward in t typ = 40 ms to the run frequency set by a resistor at the pin rfm to gnd. the saturation control is activated if the sensed slope at the lscs pin reaches typically 205 mv/s 25 mv/s and exceeds the 0.8 v threshold. this stops the frequency decreasing and signifies waiting for an adequate output voltage. the saturation control is now continuously monitored by the lscs pin. the maximum duration of the saturation control procedure is limited to 237 ms. if there is still saturation within this time frame, the saturation control is disabled and the ic changes over to the latched fault mode. furthermore, in order to reduce the choke size, the saturation control is designed to operate with a choke in magnetic saturation of the resonant during start-up. for an operation in magnetic saturation during saturation control mode, the voltage at the shunt at the lscs pin 2 has to be v lscs = 0.80 v when the output voltage is reached. if the saturation control mode is successfully passed, the ic enters the extended saturation mode the extended saturation mode is a safety mode used in order to prevent a malfunction of the ic due to an instable system. after 625 ms, the ic changes to the run mode ( start-up procedure from soft start to run mode figure 7). the run mode monitors the complete system regarding bus over- and under voltage, open loop, overcurrent of pfc and/or inverter, output overvoltage, over temperature and capacitive load operation .
icl5101 functional description datasheet 15 rev. 1.2, 2015-09-23 2.2 detection stage 2.2.1 detection of over temperature force a shut-off of the ic due to over temperature by using a ptc to gnd on pin 11. in the event of an over temperature of the system (in run mode), the current out of the otp pin 11 i otp3 = - 21.3 a charges up a capacitor. if the voltage at the otp pin 11 exceeds the v otp3 = 3.2v threshold, the controller detects an over temperature and stops the gate drives after a delay of t = 620s set by an internal timer. the system restarts automatically. the possibility of a latch of the system is happen when it cools down and heat up within 200ms. when system is too hot before startup, the system prevents a power up. 2.2.2 detection of output overvoltage overvoltage is detected by measuring the peak levels of the voltage at the aux winding via an ac current fed into the ovp pin 12. if the sensed ac current exceeds 210 a pp for longer than 620 s, the status of overvoltage is detected. the ovp fault results in a latched power-down mode (after trying a single restart). the controller continuously monitors the status until the overvoltage status changes. 2.2.3 detection of capacitive mode operation resonant converter designs should avoid working in capacitive mode operation ?not even under abnormal conditions. icl5101 provides capacitive mode operation detection and latch-off of the system after a single restart for error verification. resonant converters work in capacitive mode when their switching frequency falls below a critical value. this depends on the loading condition and the input-to-output ratio. they are especially prone to enter capacitive mode when the input voltage is lower than the minimum specified and/or the output is overloaded or shorted. in order to prevent a malfunction in the area of capacitive load during run mode due to certain deviations from the normal load, the ic senses only via the lscs pin 2. capacitive load operation is detected if the voltage at the lscs pin drops below a second threshold of v lscs = ? 50 mv directly before the high-side mosfet is turned on or exceeds a third threshold of v lscs = 2.0 v during on switching of the high-side mosfet (see capacitive mode operation figure 8). if this overcurrent is present for longer than 620 s, the ic results a latched power-down mode after trying a single restart. figure 8 capacitive mode operation
icl5101 functional description datasheet 16 rev. 1.2, 2015-09-23 2.2.4 surge protection description surge protection in case of a surge event, the voltage at the bus capacitors c5 & c8 rises up, the driver stages of the icl5101 are shut off when v lscs > 0.8v and v bus > 109% for longer than 500ns. after the surge the controller restarts automatically when v bus drops below 109% of the rated voltage. this feature allows driving 500v mosfets at the half bridge stage when adequate emi and dc link networking is present. surge detection if the bus voltage exceeds: v bus > 109% and the voltage at the low side current sense pin 2 exceeds: v lscs > 0.8v for longer than t = 500ns surge protection all gate drives off auto restart: v bus < 109% measurement surge event of 1.7kv without varistor vr1 figure 9 : surge 1.7 kv / full load / detail l ? n / phase: 90 ch 1 dark blue: v lscs ls current sense to ic gnd ch 2 blue: v bus to power gnd ch 3 magenta: v lsds ls drain to power gnd ch 4 green: v pfcds pfc drain to power gnd figure 10 : surge 1.7 kv / full load / auto restart l ? n / phase: 90 ch 1 dark blue: v lscs ls current sense to ic gnd ch 2 blue: v bus to power gnd ch 3 magenta: v lsds ls drain to power gnd ch 4 green: v pfcds pfc drain to power gnd surge event: v bus > 109% & v lscs > 800mv auto restart:v bus < 10 9 %
icl5101 functional description datasheet 17 rev. 1.2, 2015-09-23 2.2.5 self-adapting dead time during gate drive activity between hs and ls the dead time between the turn off and turn on of the resonant drivers is self-adapting and is detected by means of switch-off of the high-side mosfet and the ?50 mv threshold of the lscs voltage (see figure 11figure 11). the typical range of the dead time adjustment is 500 ns up to 1.0 s during all operating modes. the start of the dead time measurement is the off switching of the high-side mosfet. the dead time measurement finishes when v lscs drops below -50 mv for longer than typically 300 ns (internal fixed propagation delay). this time will be stored (= stored dead time) and the low-side gate driver switches on. the high-side gate driver turns on again after off switching of the low-side switch and the stored dead time. figure 11 dead time on and off of the inverter gate drivers
icl5101 functional description datasheet 18 rev. 1.2, 2015-09-23 2.2.6 short term bus under voltage short-term pfc bus under voltage (figure 12)is detected if the duration of the under voltage does not exceed 800 ms (timer remains below t < 800 ms). in this case, the pfc and inverter drivers are immediately switched off and the controller continuously monitors the status of the bus voltage in a latched power-down mode (i cc < 170 a). if the signal at the ovp pin exceeds 18 a and the rated bus voltage is above 12.5 % while the timer is below t < 800 ms, the controller restarts from power-up. the timer resets to 0 when entering the run mode. figure 12 bus under voltage ? short s a t u r a t i o n c o n t r o l
icl5101 functional description datasheet 19 rev. 1.2, 2015-09-23 2.2.7 long-term bus under voltage if the bus under voltage exceeds t > 800 ms (see figure 13 fehler! verweisquelle konnte nicht gefunden werden. ), the controller forces an under voltage lock-out (uvlo). the chip supply voltage drops below v cc = 10.6 v and the chip supply current is below i cc < 130 a. when the vcc voltage exceeds the 10.6 v threshold again, the ic current consumption is below i cc < 160 a. in this case, the controller resets the timer and restarts with the full start-up procedure, including monitoring, power-up, start-up, soft start, saturation control, extended saturation mode and run mode. figure 13 bus under voltage ? long 95% 75% v busrated v cc 16v i out i cc < 6 ma + i gate < 160 a < 6 ma + i gate interrupt for t > 800 ms timer t = 800ms uvlo @ 10.6v bus voltage drop for t > 800 ms restart with full start procedure run mode power down mode uvlo monitoring power up start up soft start saturation control extended saturation control run mode <160 a
icl5101 functional description datasheet 20 rev. 1.2, 2015-09-23 2.3 pfc preconverter 2.3.1 operation modes of the pfc converter the digitally controlled pfc preconverter starts with an internally fixed on time of typically t on = 4.0s and variable frequency. the on time is increased every 280 s (typical) up to a maximum on time of 24 s. the control switches quite immediately from discontinuous conduction mode (dcm) to critical conduction mode (crcm) as soon as a sufficient zcd signal becomes available. the frequency range in crcm is 22 khz up to 500 khz, depending on the power (figure 14 pfc dcm / crcm vs power and on time fehler! verweisquelle konnte nicht gefunden werden. ) with a variation in the on time of 24 s > t on > 0.5s. figure 14 pfc dcm / crcm vs power and on time for lower loads (p outnorm < 8 % of the normalized load 1 ) the controller operates in discontinuous conduction mode (dcm) with an on time of 4.0 s and increasing off time. the frequency during dcm is variable in a range from 144 khz down to typically 22 khz @ 0.1 % load. with this control method, the pfc converter enables stable operation from a 100 % load down to 0.1 %. figure 14 pfc dcm / crcm vs power and on time) shows the on time range in dcm and crcm (critical conduction mode) operation. in the overlapping area of crcm and dcm there is a hysteresis of the on time, which causes a negligible frequency change. 1 normalized power @ low line input voltage and maximum lload discontinuous conduction mode (dcm) <> critical condution mode (critcm) 0,01 0,10 1,00 10,00 100,00 1000,00 0,01 0,10 1,00 10,00 100,00 normalized output power [% ] p f c f r e q u e n c y [ k h z ] 5 0 % d u t y c y c l e 0,10 1,00 10,00 100,00 p f c - o n t i m e [ s ] frequency dcm frequency critcm ton dcm ton critcm
icl5101 functional description datasheet 21 rev. 1.2, 2015-09-23 2.3.2 pfc bus overvoltage and open loop the bus voltage loop control is completely integrated (figure 15 pfc bus voltage operating and error levels) and provided by an 8-bit sigma-delta a/d converter with a typical sampling rate of 280 s and a resolution of 4 mv/bit. after leaving monitoring, the ic starts to power up (v cc > 14.0 v). after power-up, the ic senses the bus voltage below 12.5 % (open loop) or above 105 % (bus overvoltage) for 80 s ? 130 s. in the case of bus overvoltage (v busrated > 109 %) or open loop (v busrated < 12.5 %), the ic shuts off the gate drives of the pfc within 5 s or 1 s respectively. in this case, the pfc restarts automatically when the bus voltage is within the corridor (12.5 % < v busrated < 105 %) again. if the bus voltage is valid after the 130 s, the bus voltage sensing is set to 12.5 % < v busrated < 109 %. if these thresholds are departed from for longer than 1 s (open loop) or 5 s (overvoltage), the pfc gate drive stops working until the voltage drops below 105 % or exceeds the 12.5 % level. if the bus overvoltage (> 109 %) lasts for longer than 625 ms in run mode, the inverter gates also shut off and a power-down with complete restart is attempted (figure 15 pfc bus voltage operating and error levels fehler! verweisquelle konnte nicht gefunden werden. ). figure 15 pfc bus voltage operating and error levels 2.3.3 pfc bus voltage levels 95 % and 75 % when the rated bus voltage is in the corridor of 12.5 % < v busrated < 109 %, the ic will check whether the bus voltage exceeds the 95 % threshold (figure 15 pfc bus voltage operating and error levels fehler! verweisquelle konnte nicht gefunden werden. ) within 80 ms before entering soft start phase. another threshold is activated when the ic enters the run mode. if the rated bus voltage drops below 75 % for longer than 84 s, a power-down with a complete restart is attempted if a counter exceeds 800 ms. in the case of short-term bus under voltage (the bus voltage reaches its working level in run mode before exceeding typically 800 ms - min. 500 ms) the ic skips phases and starts up directly in saturation control. the internal reference level of the bus voltage sense v pfcvs is 2.5 v (100 % of the rated bus voltage) with a high accuracy. surge protection is activated in the case of a rated bus voltage of v bus > 109 % and a low-side current sense voltage of v lscs > 1.6 v in extended saturation mode or of v lscs > 0.8 v in run mode for longer than 500 ns in run mode.
icl5101 functional description datasheet 22 rev. 1.2, 2015-09-23 2.3.4 pfc structure of mixed signals a digital notch filter eliminates the input voltage ripple independent of the mains frequency. a subsequent error amplifier with pi characteristic ensures stable operation of the pfc preconverter (figure 16 pfc mixed signal structure fehler! verweisquelle konnte nicht gefunden werden. ). figure 16 pfc mixed signal structure the zero current detection (zcd) is sensed by the pfc zcd. indication of finished current flow during demagnetization is required in crcm and in dcm as well. the input is equipped with a special filtering, including an extended saturation of typically 500 ns and a large hysteresis of typically 0.5 v and 1.5 v v pfczcd .
icl5101 functional description datasheet 23 rev. 1.2, 2015-09-23 2.3.5 thd correction via zero crossing detection singal an additional feature is the thd correction (figure 17 thd improvement ? automatic pulse width fehler! verweisquelle konnte nicht gefunden werden. ). in order to optimize the thd (especially in the zones a shown in fehler! verweisquelle konnte nicht gefunden werden. , zcd @ ac input voltage), there is a possibility to extend the pulse width of the gate signal (blue part of the pfc gate signal) via the variable pfc zcd resistor from the zcd pin to the pfc choke in addition to the gate signal controlled by the v pfcvs signal (gray part of the pfc gate signal). figure 17 thd improvement ? automatic pulse width extension in the case of dc input voltage, the pulse width gate signal is fixed as a combination of the gate signal controlled by the v pfcvs pin (gray) and the additional pulse width signal controlled by the zcd pin (blue) zcd @ dc input voltage. the pfc current limitation at pin pfccs interrupts the on time of the pfc mosfet if the voltage drop at the pfc shunt resistors exceeds v pfccs = 1.0 v. this interrupt will restart after the next sufficient signal from zcd becomes available (auto restart). the first value of the resistor can be calculated as the ratio of the pfc mains choke and zcd winding times the bus voltage to a current of typically 1.5 ma (see equation below). an adjustment of the zcd resistor causes an optimized thd. ma v n n r bus pfc zcd zcd 5 . 1 * ? equation 1: r zcd ? a good practical value rectified ac input voltage 0 voltage at zcd-winding dc input voltage 0 0 pfc gate drive voltage a b a zcd @ dc input voltage zcd @ ac input voltage pfc gate signal (gray) controlled by the v pfcvs pfc gate signal (blue) controlled by the zcd
icl5101 functional description datasheet 24 rev. 1.2, 2015-09-23 thd adujstment introduction: in order to provide an excellent thd result, the thd of the icl5101 is adjustable. especially at high line input voltage and low load condition, the thd is a critical value. it doesnt matter in which condition: - line input voltage - stable load - load variation the icl5101 is providing best results for all cases ? only by trimming a resistor r3 see figure 18 . figure 18 principle schematic icl5101 figure 19 pin setup icl5101 r 8 r f m n . a . n . a . v c c o v p g n d i c l 5 1 0 1 o t p v r 1 ? r 1 1 i c l 5 1 0 1
icl5101 functional description datasheet 25 rev. 1.2, 2015-09-23 how to do: to improve the thd the resistor ? see r3 figure 18 or red signed resistor in figure 19 ? at zcd pin 7 can be trimmed to an optimal value (several k-ohm ~ 20 up to 100k) in order to reach best thd results. step one is to define the inductivity of the pfc choke and the mosfet. after fixing pfc choke and transistor, two scenarios are happen: 1/ operation in stable load condition e.g. lamp on / off set nominal load condition and vary the value of the resistor until you get the best thd results. outcome sees figure 20 black curve 2/ operation with load variation e.g. dimming of an led choose a resistor and vary the load. change value up or down in order to get your best result over the whole load range ? outcome sees figure 20 red curve. mechanism: the controller operates in two modes: - critical conduction mode (crcm) in a wide load range - wait cycle mode (wcm ? a kind of dcm) for low load switch from crcm into wcm): the icl5101 has an integrated logic which can be regulated via the resistor at the zcd pin 7 in varying the value of the resistor. limit: the digital logic of the controller is limited. at high line input voltages, the controller reduces the on time of the pfc gate driver. if the minimum on time is reached ? physically given by the internal digital stage ? the controller switches over from the critical conduction mode crcm into the wait cycle mode wcm. this switch over can be seen in the thd measurement shown in figure 20 black curve. depending on the load (stable or variable) the optimum configuration can be found as shown in figure 20 red curve. this effect can be prevented by trimming the resistor at the zcd pin 7 ? lower the resistance leads to a smother cross over from crcm into wcm (red curve) but increases slightly the thd. figure 20 mode switching in stable or vary load condition 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 t h d [ % ] load[%] thd vs. load @ v acin = 230 using diff. r zcd 110w board t h d [ % ] 3 9 k ? t h d [ % ] 5 1 k ? r zcd = 5 1 k ? i d e a l f o r s t a b l e l o a d c o n d i t i o n s mode change from critcm into wcm r zcd = 3 9 k ? i d e a l f o r v a r y l o a d c o n d i t i o n s smooth mode change limit starting thd is higher
icl5101 functional description datasheet 26 rev. 1.2, 2015-09-23 2.4 state diagram 2.4.1 monitoring of features versus operating mode figure 21 monitoring of features versus operation mode
icl5101 functional description datasheet 27 rev. 1.2, 2015-09-23 2.4.2 fault condition ? flow chart fault f latch off / single restart / restart figure 22 fault condition ? flow chart latch off / single restart / restart inverter and pfc gate off only at inverter over current pfc gate off appr. 150s delayed power down icc < 160a wait 200ms delay timer 1 fault counter < 2 power-up n n y vcc < 10.6v? n y vcc > 14.0v? wait for v otp > 1.3v v otp < 3.2v v otp < 1.3v v otp > 3.2v y n uvlo reset all latches & counters reset flag skip start up procedure v otp > 1.3v v otp < 3.2v wait 100ms y fault a auto restart surge time out start up (vbus < 95% for t > 80 ms) y n fault a timeout 80ms start-up y n t > 80ms? from power-up end start-up v bus > 95%? start-up inverter gates on pfc gate on 17.5v> vcc >10.6v f_inv = f_fixed
icl5101 functional description datasheet 28 rev. 1.2, 2015-09-23 2.4.3 fault condition ? flow chart fault a auto restart figure 23 fault condition ? auto restart inverter and pfc gate off only at inverter over current pfc gate off appr. 150s delayed power down icc < 160a wait 200ms delay timer 1 fault counter < 2 power-up n n y vcc < 10.6v? n y vcc > 14.0v? wait for v otp < 1.3v v otp < 1.3v n y uvlo reset all latches & counters reset flag skip start up procedure v otp < 1.3v wait min 100ms y fault a auto restart surge time out start up (vbus < 95% for t > 80 ms) y n fault a timeout 80ms start-up y n t > 80ms? from power-up end start-up v bus > 95%? start-up inverter gates on pfc gate on 17.5v> vcc >10.6v f_inv = f_fixed
icl5101 functional description datasheet 29 rev. 1.2, 2015-09-23 2.4.4 fault condition ? flow chart fault u bus voltage figure 24 fault condition ? auto restart
icl5101 functional description datasheet 30 rev. 1.2, 2015-09-23 2.4.5 protection matrix description of fault characteristics of fault operating mode detection is active consequence n a m e o f f a u l t t y p e o f f a u l t m i n i m u m d u r a t i o n o f e f f e c t m o n i t o r i n g p o w e r - u p 1 3 0 s s t a r t - u p u n t i l v b u s > 9 5 % s o f t s t a r t 1 1 m s s a t u r a t i o n c o n t r o l 4 0 m s t y p . e x t . s a t . c o n . 6 2 5 m s r u n m o d e supply voltage vcc < 14.1v before power up below start-up threshold s 1s x prevents power up supply voltage vcc < 10.6v after power up below uvlo threshold s 5s x x x x x x x power down, reset failure latch voltage at otp pin > 1.6v before power up overtemperature s 100s x prevents power up voltage at otp pin > 3.2v overtemperature f 620s x power down, latched fault mode, 1 restart bus voltage < 12.5% of rated level 10s after power up open loop detection s 1s x keep gate drives off, re- start after vcc hysteresis bus voltage < 12.5% of rated level open loop detection n 1s x x x x x stops pfc fet until vbus > 12.5% bus voltage < 12.5% of rated level shutdown option u 625ms x power down, restart when vbus> 12.5% bus voltage < 75% of rated level add. shut down delay 120s under voltage u 84s x power down, 100ms delay, restart directly with saturation control bus voltage < 95% of rated level during start-up timeout max start-up time a 80ms x power down, 200ms delay, restart bus voltage > 105% of rated level 10s after power up pfc overvoltage s 5s x keep gate drives off, re- start after vcc hysteresis bus voltage > 109% of rated level in active operation pfc overvoltage n 5s x x x x x stops pfc fet until vbus< 105% bus voltage > 109% of rated level in active operation inverter overvoltage u 625ms x power down, restart when vbus<105% peak level of output voltage at pin ovp above threshold output overvoltage f 620s x power down, latched fault mode, 1 restart capacitive load operation below resonance overload f 620s x power down, latched fault mode, 1 restart voltage at pfccs pin > 1.0v pfc overcurrent n 200ns x x x x x stops on-time of pfc fet immediately voltage at lscs pin > 0.8v inverter current lim n 200ns x activates saturation control voltage at lscs pin > 1.2v & 205mv/s slope in 0.8v saturation time out f 237ms x power down, latched fault mode, 1 restart voltage at lscs pin > 0.8v & 205mv/s slope ext. sat. time out f 625ms x power down, latched fault mode, 1 restart voltage at lscs pin > 0.8v inverter overcurrent f 500ns x power down, latched fault mode, 1 restart voltage at lscs pin > 1.6v inverter overcurrent f 500ns x x x x power down, latched fault mode, 1 restart voltage at lscs pin > 0.8v & vbus > 109% (surge) inverter overcurrent a 500ns x x power down, restart when vbus<109% after jump into latched fault mode f wait 200ms a single restart attempt after delay of internal timer reset of failure latch in run mode after 40s reset of failure latch by uvlo or 40s in run mode s = start-up condition, n = no fault, a = auto restart , u = under voltage f = fault with a single restart, a second f leads to a latched fault / note: all values @ typical 50 hz mains frequency
icl5101 electrical characteristics datasheet 31 rev. 1.2, 2015-09-23 3 electrical characteristics note: all voltages without the high-side signals are measured with respect to ground (pin 4). the high-side voltages are measured with respect to pin 17. the voltage levels are valid if other ratings are not violated. 3.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which if exceeded may lead to destruction of the integrated circuit. for the same reason make sure that any capacitor connected to pin 3 (v cc ) and pin 18 (hsvcc) is discharged before assembling the application circuit. parameter symbol limit values unit remarks min. max. lscs voltage v lscs - 5 6 v lscs current i lscs - 3 3 ma lsgd voltage v lsgd - 0.3 v cc +0.3 v internally clamped to 11v lsgd peak source current i lsgdsomax - 75 5 ma < 500 ns lsgd peak sink current i lsgdsimax - 50 400 ma < 100 ns vcc voltage v vcc - 0.3 18.0 v vcc zener clamp current i vcczener - 5 5 ma ic in power down mode pfcgd voltage v pfcgd - 0.3 v cc +0.3 v pfcgd peak source current i pfcgdsomax - 150 5 ma < 500 ns pfcgd peak sink current i pfcgdsimax - 100 700 ma < 100 ns pfccs voltage v pfccs - 5 6 v pfccs current i pfccs - 3 3 ma pfczcd voltage v pfczcd - 3 6 v pfczcd current i pfczcd - 5 5 ma pfcvs voltage v pfcvs - 0.3 5.3 v rfm voltage v rfm - 0.3 5.3 v otp voltage v otp - 0.3 5.3 v ovp voltage v ovp - 6 7 v ovp current1 i ovp_1 - 1 1 ma ic in power down mode ovp current2 i ovp_2 - 3 3 ma ic in active mode hsgnd voltage v hsgnd - 650 650 v referring to gnd 1) hsgnd voltage transient dv hsgnd /dt - 40 40 v/ns hsvcc voltage v hsvcc - 0.3 18.0 v referring to hsgnd 1) limitation due to voltage capability in end test
icl5101 electrical characteristics datasheet 32 rev. 1.2, 2015-09-23 parameter symbol limit values unit remarks min. max. hsgd voltage v hsgd - 0.3 v hsvcc +0.3 v internally clamped to 11v hsgd peak source current i hsgdsomax - 75 0 ma < 500ns hsgd peak sink current i hsgdsimax 0 400 ma < 100ns junction temperature t j - 40 150 c storage temperature t s - 55 150 c maximum power dissipation p tot ? 1 w pg_dso-16-23 / t amb =25c thermal resistance (2 chips) junction - ambient r thja ? 125 k/w pg_dso-16-23 @ ta = 85c & pcb area > 30x20mm soldering temperature wave ? 260 c wave soldering 1) soldering temperature reflow ? 2) c reflow soldering esd capability hbm v esd_hbm ? 2 kv human body model 3) esd capability cdm v esd_cdm ? 1 kv charged device model 4) rated bus voltage (95%) v pfcvs95 2.33 2.43 v 1) according to jesd22a111 2) according to j-std-020d 3) according to eia/jesd22-a114-b 4) according to jesd22-c101
icl5101 electrical characteristics datasheet 33 rev. 1.2, 2015-09-23 3.2 operating range the ic operates as described in the functional description once the values listed here lie within the operating range. parameter symbol limit values unit remarks min. max. hsvcc supply voltage v hsvcc v hsvccoff 17.5 v referring to hsgnd hsgnd voltage v hsgnd - 650 650 v referring to gnd 1) vcc voltage @ 25c v vcc v vccoff 17.5 v t j = 25c vcc voltage @ 125c v vcc v vccoff 18.0 v t j = 125c lscs voltage range v lscs - 4 5 v in active mode pfcvs voltage range v pfcvs 0 4 v pfccs voltage range v pfccs - 4 5 v in active mode pfzcd current range i pfczcd - 3 3 ma in active mode ovp voltage range v ovp - 6 6 2) v ovp, current range i ovp 3) 210 a ic power down mode ovp, current range i ovp - 2.5 2.5 ma ic active mode junction temperature t j - 40 125 c adjustable run frequency f rfm 20 120 khz range set by rfm adjustable run frequency f rfm 20 130 khz @ - 25c set resistor for run freq. r rfm 4.1 25 k ? mains frequency f mains 45 65 hz notch filter operation 1) limitation due to creeping distance between the hs & ls pins (ctt 900v inside) 2) limited by maximum of current range at ovp 3) limited by minimum of voltage range at ovp
icl5101 electrical characteristics datasheet 34 rev. 1.2, 2015-09-23 3.3 characteristics power supply section note: the electrical characteristics involve the spread of values given within the specified supply voltage and junction temperature range t j from -40 c to 125 c. typical values represent the median values, which are given in reference to 25 c. if not otherwise stated, a supply voltage of 15 v and v hsvcc = 15 v is assumed and the ic operates in active mode. furthermore, all voltages refer to gnd if not otherwise mentioned. parameter symbol limit values unit test condition min. typ. max. vcc quiescent current1 i vccqu1 ? 90 130 a v vcc = v vccoff ? 0.5v vcc quiescent current2 i vccqu2 ? 120 160 a v vcc = v vccon ? 0.5v vcc supply current 1) i vccsupply ? 4.2 6.0 ma v pfcvs > 2.725v vcc supply current in latched fault mode i vcclatch ? 110 170 a v otp = 5v lsvcc turn-on threshold lsvcc turn-off threshold lsvcc turn-on/off hyst. v vccon v vccoff v vcchys 13.48 10.0 3.2 14.0 10.6 3.6 14.5 11.0 4.0 v v v hysteresis vcc zener clamp voltage v vccclamp 15.5 16.3 16.9 v i vcc = 2ma/v otp = 5v vcc zener clamp current i vcczener 2.5 ? 5.05 ma v vcc = 17.5v/v otp = 5v high side leakage current i hsgndleak ? 0.01 2 a v hsgnd = 650v, v gnd =0v hsvcc quiescent current i hsvccqu1 2) ? 190 280 a v hsvcc = v hsvccon ? 0.5v hsvcc quiescent current 1) i hsvccqu2 2) 0.26 0.65 1.2 ma v hsvcc > v hsvccon hsvcc turn-on threshold hsvcc turn-off threshold hsvcc turn-on/off hyst. v hsvccon 2) v hsvccoff 2) v hsvcchy 2) 9.75 8.08 1.4 10.4 8.6 1.7 11.0 9.3 2.03 v v v hysteresis low side ground gnd 1) with inactive gate 2) refers to high-side ground (hsgnd) 3.4 characteristics of pfc section 3.4.1 pfc current sense (pfccs) parameter symbol limit values unit test condition min. typ. max. turn-off threshold v pfccsoff 0.95 1.0 1.05 v overcurrent blanking + propagation delay 1) t pfccsoff 140 200 262 ns leading-edge blanking t blanking 180 250 315 ns pulse width when v pfccs > 1.0v pfccs bias current i pfccsbias - 0.5 ? 0.5 a v pfccs = 1.5v 1) propagation delay = 50 ns
icl5101 electrical characteristics datasheet 35 rev. 1.2, 2015-09-23 3.4.2 pfc zero current detection (pfczcd) parameter symbol limit values unit test condition min. typ. max. zero crossing upper thr. 1) v pfczcdup 1.4 1.5 1.6 v zero crossing lower thr. 2) v pfczcdlow 0.4 0.5 0.6 v zero crossing hysteresis v pfczcdhys ? 1.0 ? v clamping of pos. voltages v pfczcdpclp 4.1 4.6 5.12 v i pfczcdsink = 2ma clamping of neg. voltages v pfczcdnclp - 1.69 - 1.4 - 1.0 v i pfczcdsource = - 2ma pfczcd bias current i pfczcdbias - 0.5 ? 5.0 a v pfczcd = 1.5v pfczcd bias current i pfczcdbias - 0.5 ? 0.5 a v pfczcd = 0.5v pfczcd ringing su. 3) time t ringsup 350 500 660 ns limit value for on time extension t x i zcd 498 700 900 paxs 1) turn-off threshold 2) turn-on threshold 3) ringing suppression time 3.4.3 pfc voltage sensing bus (pfcvs) parameter symbol limit values unit test condition min. typ. max. trimmed reference voltage v pfcvsref 2.468 2.50 2.53 v overvoltage turn-off (109 %) v pfcvsrup 2.677 2.73 2.78 v overvoltage turn-on (105 %) v pfcvslow 2.567 2.63 2.68 v overvoltage hysteresis v pfcvshys 70 100 130 mv 4 % rated bus voltage under voltage (75 %) v pfcvsuv 1.832 1.88 1.915 v under voltage (12.5 %) v pfcvsuv 0.237 0.31 0.387 v rated bus voltage (95 %) v pfcvs95 2.320 2.38 2.425 v pfcvs bias current i pfcvsbias - 1.0 ? 1.0 a v pfcvs = 2.5v 3.4.4 pfc pwm generation parameter symbol limit values unit test condition min. typ. max. initial on time 1) t pfcon_initial ? 4.0 ? s v pfczcd = 0v max. on time 2) t pfcon_max 18.0 24.0 28.6 s 0.45v < v pfcvs < 2.45v switch threshold from crcm to dcm t pfcon_min 160 270 370 ns repetition time 1) t pfcrep 47 52 57 s v pfczcd = 0v off time t pfcoff 42 47 52.5 s 1) when missing zero crossing signal 2) at the maximum of the ac line input voltage
icl5101 electrical characteristics datasheet 36 rev. 1.2, 2015-09-23 3.4.5 pfc gate drive (pfcgd) parameter symbol limit values unit test condition min. typ. max. pfcgd low voltage v pfcgdlow 0.4 0.7 0.92 v i pfcgd = 5ma 0.4 0.75 1.12 v i pfcgd = 20ma - 0.2 0.3 0.62 v i pfcgd = -20ma pfcgd high voltage v pfcgdhigh 10.0 11.0 11.6 v i pfcgd = -20ma 8.98 ? ? v i pfcgd = -1ma / v vcc 1) 8.47 ? ? v i pfcgd = -5ma / v vcc 1) pfcgd active shut down v pfcgasd 0.4 0.75 1.12 v i pfcgd = 20ma v vcc =5v pfcgd uvlo shut down v pfcgduvlo 0.3 1.0 1.56 v i pfcgd = 5ma v vcc =2v pfcgd peak source current i pfcgdsouce ? - 100 ? ma 2) + 3) pfcgd peak sink current i pfcgdsink ? 500 ? ma 2) + 3) pfcgd voltage during sink current v pfcgdhigh 11.0 11.7 12.3 v i pfcgdsinkh = 3ma pfc rise time t pfcgdrise 80 245 500 ns 2v > vlsgd > 8v 2) pfc fall time t pfcgdfall 20 45 72 ns 8v > vlsgd > 2v 2) 1) v vcc = v vccoff + 0.3v 2) r load = 4 ? a n d c load = 3.3nf 3) the parameter is not subject to production testing ? verified by design/characterization 3.5 characteristics of inverter section 3.5.1 low-side current sense (lscs) parameter symbol limit values unit test condition min. typ. max. overcurrent shutdown volt. v lscsovc1 1.5 1.6 1.7 v 1) overcurrent shutdown volt . v lscsovc2 0.75 0.8 0.85 v 2) duration of overcurrent t lscsovc 450 600 700 ns capacitive mode det. level1 v lscscap1 - 70 - 50 - 27 mv capacitive mode duration1 t lscscap1 ? 280 ? ns 3) capacitive mode det. level2 v lscscap2 1.8 2.0 2.2 v during run mode capacitive mode duration2 t lscscap2 ? 50 ? ns 4) lscs bias current i lscsbias -1.0 ? 1.0 a @ v lscs = 1.5 v 1) overcurrent voltage threshold active during start-up, soft start, saturation control and extended saturation mode 2) overcurrent voltage threshold active during run mode 3) active before turn-on of the hsgd in run mode 4) active during turn-on of the hsgd in run mode
icl5101 electrical characteristics datasheet 37 rev. 1.2, 2015-09-23 3.5.2 low-side gate drive (lsgd) parameter symbol limit values unit test condition min. typ. max. lsgd low voltage v lsgdlow 0.4 0.7 1.02 v i lsgd = 5 ma 1) 0.4 0.8 1.22 v i lsgd = 20 ma 1) - 0.3 0.2 0.53 v i lsgd = - 20 ma (source) lsgd high voltage v lsgdhigh 10.0 10.8 11.6 v 2) 8.98 ? ? v 3) 8.47 ? ? v 4) lsgd active shutdown v lsgdasd 0.4 0.75 1.12 v v cc = 5 v / i lsgd = 20 ma 1) lsgd uvlo shutdown v lsgduvlo 0.3 1.0 1.6 v v cc = 2 v / i lsgd = 5 ma 1) lsgd peak source current i lsgdsource ? - 50 ? ma 5) + 6) lsgd peak sink current i lsgdsink ? 300 ? ma 5) + 6) lsgd voltage during 1) v lsgdhigh ? 11.7 ? v i lsgdsinkh = 3 ma lsgd rise time t lsgdrise 80 245 500 ns 2 v < v lsgd < 8 v 5) lsgd fall time t lsgdfall 20 35 61 ns 8 v > v lsgd > 2 v 5) 1) sink current 2) i lsgd = ?20 ma source current 3) v ccoff + 0.3 v and i lsgd = ?1 ma source current 4) v ccoff + 0.3 v and i lsgd = ?5 ma source current 5) load: r load = 1 0 ? a n d c load = 1 nf 6) the parameter is not subject to production testing ? verified by design/characterization 3.5.3 inverter minimum run frequency (rfm) parameter symbol limit values unit test condition min. typ. max. fixed start-upfrequency f startup 120 135 148.5 khz duration of soft start t softstart 9 11 13.56 ms 1) rfm voltage in run mode v rfm ? 2.5 ? v @ 100a icl5101 electrical characteristics datasheet 38 rev. 1.2, 2015-09-23 3.5.4 overtemperature protection (otp) parameter symbol limit values unit test condition min. typ. max. over temperature detection v otp1 1.546 1.60 1.65 v uvlo, v cc < v ccon v otp2 1.247 1.30 1.35 v v otp3 ? 3.2 ? v run mode otp current source i otp1 - 53.2 -42.6 -30.5 a v otp = 1v ; ovp = 5a i otp2 -44.2 -35.4 -25.1 a v otp = 2v ; ovp = 5a i otp3 - 26.6 -21.3 - 15.0 a v otp = 1v ; ovp = 30a i otp4 - 22.1 -17.7 -12.3 a v otp = 2v ; ovp = 30a 3.5.5 overvoltage protection (ovp) parameter symbol limit values unit test condition min. typ. max. source current before start-up i ovpenable - 5.0 - 3.0 - 1.9 a v ovp = 0v / v cc < 14.0v enable monitoring v ovpenable 350 530 750 mv 1) sink current for ovp i ovpsink 7.0 12.0 18.0 a v cc < 14.0v positive clamping voltage v ovpclamp ? 6.5 ? v @ i ovp = 300a ac ovp current threshold i ovpsource 186 210 230 app 1) if v ovp < v ovpenable monitoring is disabled
icl5101 electrical characteristics datasheet 39 rev. 1.2, 2015-09-23 3.5.6 high side gate drive (hsgd) parameter symbol limit values unit test condition min. typ. max. hsgd low voltage v hsgdlow 0.018 0.05 0.1 v i hsgd = 5ma (sink) 0.46 1.1 2.5 v i hsgd = 100ma (sink) - 0.4 - 0.2 - 0.04 v i lsgd = - 20ma (source) hsgd high voltage v hsgdhigh 9.7 10.5 11.2 v v cchs =15v i hsgd = - 20ma (source) 7.8 ? ? v v cchsoff + 0.3v i hsgd = - 1ma (source) hsgd active shut down v hsgdasd 0.041 0.22 0.5 v v cchs =5v i hsgd = 20ma (sink) hsgd peak source current i hsgdsource ? - 50 ? ma r load = 1 0 ? + c load = 1nf 1) hsgd peak sink current i hsgdsink ? 300 ? ma r load = 1 0 ? + c load = 1nf 1) hsgd rise time t hsgdrise 120 220 300 ns 2v < v lsgd < 8v r load = 1 0 ? + c load = 1nf hsgd fall time t hsgdfall 19 35 70 ns 8v > v lsgd > 2v r load = 1 0 ? + c load = 1nf 1) the parameter is not subject to production test ? verified by design / characterization 3.6 timer section delay timer 1 t timer1 70 100 163.6 ms for fault detection delay timer 2 t timer2 74 84 94 ms for v bus > 95% inverter time t inv 100 130 163 s inverter dead time max t deadmax 0.85 1.05 1.25 s v _gd_th =2v r load = 1 0 ? + c load = 1nf inverter dead time min t deadmin 400 500 650 ns v _gd_th =2v r load = 1 0 ? + c load = 1nf i n v e r t e r d e a d t i m e m a x t deadmax - 200 ? 200 ns i n v e r t e r d e a d t i m e m i n t deadmin - 200 ? 200 ns min. duration of sat. control t saturationmin 34 40 48 ms max. duration of sat. control t saturationmax 197 ? 236 ms duration of ext. sat. mode tblm 565 625 685 ms
icl5101 application example datasheet 40 rev. 1.2, 2015-09-23 4 application example 4.1 schematic figure 25 schematic led driver using pfc / llc topology for 110w / 54v 85 ... 325 vac c2 c4 c5 c1 c7 c6 c8 r3 r5 r6 r4 r7 r2 r13 r14 r17 br1 d2 d4 l1 l2 lr q1 q2 q3 l4_1 r12 r15 cr l4_2 l4_3 d6 c11 r16 r20 r23 r24 r22 r21 c12 pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs fuse d1 r1 ic2 ic1 ot1 l4_4 c3 c9 r18 r19 d3 d5 d8 q4 d9 r9 r10
icl5101 outline dimensions datasheet 41 rev. 1.2, 2015-09-23 5 outline dimensions outline dimensions are shown in figure 26 . figure 26 pg-dso-16-23 notes 1. you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . 2. dimensions in mm.
edition 2013-11-08 published by infineon technologies ag 81726 munich, germany ? 2015 infineon technologies ag all rights reserved. legal disclaimer the infromation given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any infromation regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. infromation for further infromation on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for infromation on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
icl5101 revision history: 2015-09-23 previous revision: 2015-07-24 page or item subjects (major changes since previous revision) page 8 / 30 / 34 run frequency: 120 khz @ - 40 c / 130 khz @ - 25 c all deleted confidential 3.5.5 ovp: wrong value deleting / index adjustment all complete review pages: 2 / 40 figure updates: 1 / 25 replacement of d7 page: 24 figure updates: 18 replacement of d7 / 19 update trademarks of infineon technologies ag aurix ? , c166 ? , canpak ? , cipos ? , cipurse ? , econopack ? , coolmos ? , coolset ? , corecontrol ? , crossave ? , dave ? , di-pol ? , easypim ? , econobridge ? , econodual ? , econopim ? , econopack ? , eicedriver ? , eupec ? , fcos ? , hitfet ? , hybridpack ? , i2rf ? , isoface ? , isopack ? , mipaq ? , modstack ? , my-d ? , novalithic ? , optimos ? , origa ? , powercode ? , primarion ? , primepack ? , primestack ? , pro-sil ? , profet ? , rasic ? , reversave ? , satric ? , sieget ? , sindrion ? , sipmos ? , smartlewis ? , solid flash ? , tempfet ? , thinq! ? , trenchstop ? , tricore ? . other trademarks advance design system ? (ads) of agilent technologies, amba ? , arm ? , multi-ice ? , keil ? , primecell ? , realview ? , thumb ? , vision ? of arm limited, uk. autosar ? is licensed by autosar development partnership. bluetooth ? of bluetooth sig inc. cat-iq ? of dect forum. colossus ? , firstgps ? of trimble navigation ltd. emv ? of emvco, llc (visa holdings inc.). epcos ? of epcos ag. flexgo ? of microsoft corporation. flexray ? is licensed by flexray consortium. hyperterminal ? of hilgraeve incorporated. iec ? of commission electrotechnique internationale. irda ? of infrared data association corporation. iso ? of international organization for standardization. matlab ? of mathworks, inc. maxim ? of maxim integrated products, inc. microtec ? , nucleus ? of mentor graphics corporation. mipi ? of mipi alliance, inc. mips ? of mips technologies, inc., usa. murata ? of murata manufacturing co., microwave office ? (mwo) of applied wave research inc., omnivision ? of omnivision technologies, inc. openwave ? openwave systems inc. red hat ? red hat, inc. rfmd ? rf micro devices, inc. sirius ? of sirius satellite radio inc. solaris ? of sun microsystems, inc. spansion ? of spansion llc ltd. symbian ? of symbian software limited. taiyo yuden ? of taiyo yuden co. teaklite ? of ceva, inc. tektronix ? of tektronix inc. toko ? of toko kabushiki kaisha ta. unix ? of x/open company limited. verilog ? , palladium ? of cadence design systems, inc. vlynq ? of texas instruments incorporated. vxworks ? , wind river ? of wind river systems, inc. zetex ? of diodes zetex limited. last trademarks update 2011-11-11
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